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TECHNICAL NOTE
High Reliability Series Serial EEPROM Series
I C BUS Serial EEPROMs
BR24L-W Series
BR24L01A-W, BR24L02-W, BR24L04-W, BR24L08-W, BR24L16-W, BR24L32-W, BR24L64-W
2
BR24S-W Series
BR24S16-W, BR24S32-W, BR24S64-W, BR24S128-W, BR24S256-W
ROHM's series of serial EEPROMs represent the highest level of reliability on the market. A double cell structure provides a failsafe method of data reliability, while a double reset function prevents data miswriting. In addition, gold pads and gold wires are used for internal connections, pushing the boundaries of reliability to the limit. BR24L-W Series assort 1Kbit64Kbit. BR24S-W Series are possible to operate at high speed in low voltage and assort 16Kbit256Kbit.
Contents BR24L-W Series
BR24L01A-W, BR24L02-W, BR24L04-W, BR24L08-W, BR24L16-W, BR24L32-W, BR24L64-W
P2 BR24S-W Series
BR24S16-W, BR24S32-W, BR24S64-W, BR24S128-W, BR24S256-W
P17
Sep. 2008
I2C BUS Serial EEPROMs
BR24L-W Series BR24L01A-W, BR24L02-W, BR24L04-W, BR24L08-W, BR24L16-W, BR24L32-W, BR24L64-W
Description 2 BR24L-W series is a serial EEPROM of I C BUS interface method. Features 2 Completely conforming to the world standard I C BUS. All controls available by 2 ports of serial clock(SCL) and serial data(SDA) Other devices than EEPROM can be connected to the same port, saving microcontroller port *1 1.8V~5.5V single power source action most suitable for battery use Page write mode useful for initial value write at factory shipment Highly reliable connection by Au pad and Au wire Auto erase and auto end function at data rewrite Low current consumption *2 At write operation (5V) : 1.2mA (Typ.) At read operation (5V) : 0.2mA (Typ.) At standby operation (5V) : 0.1A (Typ.) Write mistake prevention function Write (write protect) function added Write mistake prevention function at low voltage *3 SOP8/SOP-J8/SSOP-B8/TSSOP-B8/MSOP8/TSSOP-B8J/VSON008X2030 compact package Data rewrite up to 1,000,000 times Data kept for 40 years Page write Noise filter built in SCL / SDA terminal Shipment data all address FFh
*1 *2 *3 BR24L02-WBR24L16-WBR24L32-W : 1.75.5V BR24L32-WBR24L64-W : 1.5mA Refer to following list Number of Pages Product number 8Byte BR24L01A-W BR24L02-W 16Byte BR24L04-W BR24L08-W BR24L16-W 32Byte BR24L32-W BR24L64-W
BR24L series
Capacity Bit format Type Power source Voltage SOP8 F SOP-J8 FJ SSOP-B8 TSSOP-B8 FV FVT MSOP8 FVM TSSOP-B8J FVJ VSON008 X2030 NUX
1Kbit 2Kbit 4Kbit 8Kbit 16Kbit 32Kbit 64Kbit
128x8 256x8 512x8 1Kx8 2Kx8 4Kx8 8Kx8
BR24L01A-W BR24L02-W BR24L04-W BR24L08-W BR24L16-W BR24L32-W BR24L64-W
1.85.5V 1.75.5V 1.85.5V 1.85.5V 1.75.5V 1.75.5V 1.85.5V

2/32
Absolute maximum ratings (Ta=25)
Parameter Impressed voltage symbol VCC Limits 0.3+6.5 450 (SOP8) *1 450 (SOP-J8) *2 300 (SSOP-B8) *3 330 (TSSOP-B8) *4 310 (MSOP8) *5 310 (TSSOP-B8J) *6 300 (VSON008X2030) *7 Unit V
Memory cell characteristics (Ta=25, Vcc=1.85.5V)*1
Parameter Number of data rewrite times mW
*2
Limits Min. 1,000,000 40
*1 *2
Typ.
Max.
Unit
Times Years
Permissible dissipation
Pd
Data hold years *2 Shipment data all address FFh
BR24L02/16/32-W : 1.7~5.5V Not 100% TESTED
Storage Tstg 65+125 temperature range Action Topr 40+85 temperature range Terminal voltage 0.3Vcc+1.0 *1,*2) *3,*7) When using at Ta=25 or higher, 4.5mW( , 3.0mW( 3.3mW( ),3.1mW(
*4 *5,*6)
V
Recommended operating conditions
Parameter Power source voltage Input voltage Symbol Vcc VIN
*1
Limits 1.85.5 *1 0Vcc
Unit V
to be reduced per 1
BR24L02/16/32-W : 1.7~5.5V
Electrical characteristics (Unless otherwise specified, Ta=40+85, VCC=1.85.5V) *1
Parameter "HIGH" input voltage 1 "LOW" input voltage 1 "HIGH" input voltage 2 "LOW" input voltage 2 "HIGH" input voltage 3 *3 "HIGH" input voltage 3 *4 "LOW" input voltage 3 *2 "LOW" output voltage 1 "LOW" output voltage 2 Input leak current Output leak current Current consumption at action Symbol VIH1 VIL1 VIH2 VIL2 VIH3 VIH3 VIL3 VOL1 VOL2 ILI ILO ICC1 ICC2 ISB Min. 0.7Vcc 0.3 *2 0.8Vcc 0.3 *2 0.8Vcc 0.9Vcc 0.3 1 1 Limits Typ.
*1 *5
Max. Vcc +1.0 *2 0.3 Vcc Vcc +1.0 *2 0.2 Vcc Vcc +1.0 Vcc +1.0 0.1 Vcc 0.4 0.2 1 1 2.0 *5 3.0 *6 0.5 2.0
Unit V V V V V V V V V A A mA mA A
Conditions 2.5Vcc5.5V 2.5Vcc5.5V 1.8Vcc2.5V 1.8Vcc2.5V 1.7Vcc1.8V 1.7Vcc1.8V 1.7Vcc1.8V IOL=3.0mA, 2.5VVcc5.5V, (SDA) IOL=0.7mA, 1.7VVcc2.5V, (SDA) VIN=0VVcc VOUT=0VVcc, (SDA) Vcc=5.5V,fSCL=400kHz, tWR=5ms, Byte write, Page write Vcc=5.5V,fSCL=400kHz Random read, current read, sequential read Vcc=5.5V, SDASCL=Vcc A0, A1, A2=GND, WP=GND
Standby current
Radiation resistance design is not made.
BR24L02/16/32-W : 1.75.5V, *2 BR24L16/32-W, *3 BR24L02/16-W, *4 BR24L32-W BR24L01A/02/04/08/16-W, *6 BR24L32/64-W
Action timing characteristics
Parameter
(Unless otherwise specified, Ta=40+85, VCC=1.85.5V)*1
Symbol fSCL tHIGH tLOW tR tF tHD:STA tSU:STA tHD:DAT tSU:DAT tPD tDH tSU:STO tBUF tWR tI tHD:WP tSU:WP tHIGH:WP Min. 0.6 1.2 0.6 0.6 0 100 0.1 0.1 0.6 1.2 0 0.1 1.0 FAST-MODE 2.5VVcc5.5V Typ. STANDARD-MODE 1.8VVcc5.5V Unit Min. Typ. Max. 100 kHz 4.0 s 4.7 s 1.0 s 0.3 s 4.0 s 4.7 s 0 ns 250 ns 0.2 3.5 s 0.2 s 4.7 s 4.7 s 5 ms 0.1 s 0 ns 0.1 s 1.0 s *1 BR24L02/16/32-W : 1.75.5V *2 Not 100% tested
SCL frequency Data clock "HIGH" time Data clock "LOW" time SDA, SCL rise time *2 SDA, SCL fall time *2 Start condition hold time Start condition setup time Input data hold time Input data setup time Output data delay time Output data hold time Stop condition setup time Bus release time before transfer start Internal write cycle time Noise removal valid period (SDA, SCL terminal) WP hold time WP setup time WP valid time
Max. 400 0.3 0.3 0.9 5 0.1 -
FAST-MODE and STANDARD-MODE FAST-MODE and STANDARD-MODE are of same actions, and mode is changed. They are distinguished by action speeds. 100kHz action is called STANDARD-MODE, and 400kHz action is called FAST-MODE. This action frequency is the maximum action frequency, so 100kHz clock may be used in FAST-MODE. When power source voltage goes down, action at high speed is not carried out, therefore, at Vcc=2.5V5.5V , 400kHz, namely, action is made in FASTMODE. (Action is made also in STANDARD-MODE) Vcc=1.8V~2.5V is only action in 100kHz STANDARD-MODE.
3/32
Sync data input / output timing
tR SCL tHD:STA SDA () (input) tBUF SDA (output) () tPD tDH tSU:DAT tLOW tHD:DAT tF tHIGH
SCL DATA(1) SDA D1 D0 ACK DATA(n) ACK WR WP
Stop condition
Input read at the rise edge of SCL Data output in sync with the fall of SCL
tSUWP
HDWP
Fig.1-(a) Sync data input / output timing
SCL tSU:STA
SDA
Fig.1-(d) WP timing at write execution
SCL
tHD:STA tSU:STO
DATA(1) SDA D1 D0 ACK
DATA(n) ACK tHIGH:WP tWR
START BIT
STOP BIT
WP
Fig.1-(b) Start-stop bit timing
At write execution, in the area from the D0 taken clock rise of the first DATA(1), to tWR, set WP="LOW". By setting WP "HIGH" in the area, write can be cancelled. When it is set WP="HIGH" during tWR, write is forcibly ended, and data of address under access is not guaranteed, therefore write it once again.
WR
Stop condition Start condition
SCL
SDA
D0
Write data
ACK
(n-th address)
Fig.1-(c) Write cycle timing
Fig.1-(e) WP timing at write cancel
Block diagram
*2
A0
1
*1
1Kbit~64Kbit EEPROM array
7bit 11bit 8bit 12bit 9bit 13bit 10bit
8
8bit
Vcc
*2
A1
2
Address decoder
*1
7bit 11bit 8bit 12bit 9bit 13bit 10bit
Slave - word address register
Data register
7
WP
*2
A2
3
START
STOP
Control circuit
ACK
6
SCL
GND
4
1
High voltage generating circuit
7bit : BR24L01A-W 8bit : BR24L02-W 9bit : BR24L04-W 10bit : BR24L08-W 11bit : BR24L16-W 12bit : BR24L32-W 13bit : BR24L64-W
Power source voltage detection
5
: BR24L04-W : BR24L08-W : BR24L16-W
SDA
2
A0=N.C. A0, A1=N.C. A0, A1= N.C. A2=Don't Use
Fig.2
Block diagram
Pin assignment and description
A0 A1 A2 GND 1 2 3 4 BR24L01A-W BR24L02-W BR24L04-W BR24L08-W BR24L16-W BR24L32-W BR24L64-W 8 7 6 5 Vcc WP SCL SDA Terminal name A0 A1 A2 GND SDA SCL WP Vcc Input / output Input Input Input Input / output Input Input Function
BR24L01A-W BR24L02-W BR24L04-W BR24L08-W BR24L16-W BR24L32-W BR24L64-W
Slave address setting Slave address setting Slave address setting Reference voltage of all input / output, 0V
Not connected Not connected Not used
Slave address setting Slave address setting Slave address setting
Slave and word address, Serial data input serial data output Serial clock input Write protect terminal Connect the power source.
4/32
Characteristic data (The following values are6Typ. ones.) 6
5 4 VIH1,2[V] 3 2 1 0 0 1 3 4 5 Vcc[V] Fig.3 H input voltage VIH1,2 2 6
SPEC
1 0.8
5 4 VIL1,2[V] 3 2 1 0 0 3 4 5 6 Vcc[V] Fig.4 L input voltageVIL1,2(SCL,SDA,WP) 1 2
SPEC Ta=85 Ta=-40 Ta=25
VOL1[V]
0.6
SPEC Ta=85 Ta=25
0.4 0.2
Ta=85 Ta=-40 Ta=25
Ta=-40
0 0 3 4 5 6 IOL1[mA] Fig.5 L output voltageVOL1-IOL1(VCC=2.5V) 1 2
1 0.8 0.6 VOL2[V] ILI[A]
Ta=85 Ta=25
1.2
SPEC
1.2
SPEC
1 0.8 ILO[A] 0.6 0.4 0.2 6 0 0 1 2 3 Vcc[V] 4 5 6
Ta=85 Ta=25 Ta=-40
1 0.8 0.6 0.4 0.2 0 0 1 2 3 Vcc[V] 4 5 6
Ta=85 Ta=25 Ta=-40
0.4
SPEC
0.2
Ta=-40
0 0 1 2 3 4 IOL2[mA] 5
Fig.6 L output voltage VOL2-IOL2(VCC=1.8V)
Fig.7 Input leak current ILI(SCL,WP) 3.5 0.6
[BR24L32/64 series]
Fig.8 Output leak currentILO(SDA)
2.5
[BR24L01/02/04/08/16 series] [BR24L01A/02/04/08/16 series]
SPEC
2 ICC1[mA] 1.5 1 0.5 0 0
3 2.5 ICC1[mA] 2 1.5 1 0.5 0 0
fSCL=400kHz DATA=AAh
SPEC
fSCL=400kHz DATA=AAh
SPEC
0.5 ICC2[mA] 0.4 0.3 0.2 0.1 0
fSCL=400kHz DATA=AAh Ta=85 Ta=25
Ta=25 Ta=85 Ta=-40
Ta=25 Ta=85 Ta=-40
Ta=-40
3 4 5 6 Vcc[V] Fig.9 Current consumption at WRITE action ICC1 (fscl=400kHz)
3.5
[BR24L01/02/04/08/16 series] [BR24L01A/02/04/08/16 series]
1
2
1
2
3 Vcc[V]
4
5
6
0
Fig.10 Current consumption at WRITE action ICC1 (fSCL=400kHz) 0.6
[BR24L32/64 series]
3 4 5 6 Vcc[V] Fig.11 Current consumption at READ action ICC2 (fSCL=400kHz)
SPEC
1
2
2.5 2 ICC1[mA] 1.5 1 0.5 0 0 1 2 3 Vcc[V] 4 5 6
Ta=25 Ta=85 Ta=-40
3 2.5 ICC1[mA] 2 1.5 1 0.5 0 0 1 2 3 Vcc[V] 4 5 6
Ta=25 Ta=85 Ta=-40 fSCL=100kHz DATA=AAh SPEC
0.5 ICC2[mA] 0.4 0.3 0.2
Ta=25 Ta=85 fSCL=100kHz DATA=AAh
fSCL=100kHz DATA=AAh
SPEC
0.1 0 0
Ta=-40
Fig.12 Current consumption at WRITE action ICC1 (fSCL=100kHz) 2.5
SPEC
Fig.13 Current consumption at WRITE action ICC1 (fSCL=100kHz) 10000 5
3 4 5 6 Vcc[V] Fig.14 Current consumption at READ action ICC2 (fSCL=100kHz)
SPEC2
1
2
2 ISB[A] 1.5 1 0.5 0 0 1 2 3 Vcc[V] 4 5 6
Ta=85 Ta=-40 Ta=25
1000 fSCL[kHz]
4 tHIGH [s]
Ta=85 Ta=25 Ta=-40 SPEC1 SPEC2
3 2 1 0
Ta=-40 Ta=25 Ta=85 SPEC1
100
10
1 0 1 2 3 Vcc[V] 4 5 6
0
1
2
3 Vcc[V]
4
5
6
Fig.15 Standby currentISB 5
SPEC2
Fig.16 SCL frequencyfSCL 5
SPEC2
Fig.17 Data clock "H" time tHIGH 6 5 tSU:STA[s] 4 3 2 1 0
Ta=-40 Ta=25 Ta=85 SPEC1 SPEC2
4 tHD:STA[s] tLOW[s] 3 2 1 0 0 3 4 5 Vcc[V] Fig.18 Data clock "L" time tLOW 1 2 6
Ta=85 Ta=25 Ta=-40 SPEC1
4 3 2 1 0 0 1 2 3 Vcc[V] 4 5 6
Ta=85 Ta=25 Ta=-40 SPEC1
0
1
2
3 Vcc[V]
4
5
6
Fig.19 Start condition hold timetHD:STA
Fig.20 Start condition setup time tSU:STA
5/32
Characteristic data (The following values are Typ. ones).
50
SPEC1,2
50
SPEC1,2
300 200 tSU:DAT(HIGH)[ns] 100 0
Ta=85 Ta=25 Ta=-40 SPEC2 SPEC1
tHD:DAT(HIGH)[ns]
0 -50
Ta=-40 Ta=25 Ta=85
0 tHD:DAT(LOW)[ns] -50
Ta=85 Ta=25
-100 -150 -200 0 1 2 3 Vcc[V] 4 5 6
-100 -150 -200 0 3 4 5 6 Vcc[V] Fig.22 Input data hold timetHD:DAT(LOW) 1 2
Ta=-40
-100 -200 0 1 2 3 Vcc[V] 4
5
6
Fig.21 Input data hold time tHD:DAT(HIGH) 300 200 tSU:DAT(LOW)[ns] 100 0
Ta=85 SPEC2 SPEC1
Fig.23 Input data setup timetSU:DAT(HIGH) 4
4
SPEC2
3 tPD0[s]
3 tPD1[s]
SPEC2
2
2
Ta=-40 Ta=25 Ta=85 SPEC1
Ta=85 Ta=25 Ta=-40 SPEC2 SPEC1
-100 -200 0
Ta=-40 Ta=25
1
SPEC1
1
SPEC2 SPEC1
0 1 2
0 0 1 2 3 Vcc[V] 4 5 6 0
Vcc[V]
3
4
5
6
1
2
3 Vcc[V]
4
5
6
Fig.24 Input data setup time tSU:DAT(LOW) 5
SPEC2
Fig.25 Output data delay time tPD0 6
SPEC1,2
Fig.26 Output data delay timetPD1 0.6 0.5
4 tBUF[s] tWR[ms] 3 2 1 0 0 1 2 3 Vcc[V] 4 5 6
Ta=-40 Ta=25 Ta=85 SPEC1
5
Ta=25
3 2 1 0 0 1 2
tI(SCL H)[s]
4
Ta=-40
0.4 0.3
Ta=25
Ta=-40
Ta=85
Ta=85
0.2
SPEC1,2
0.1 0 3 Vcc[V] 4 5 6 0 1 2 3 Vcc[V] 4 5 6
Fig.27 Bus release time before transfer start tBUF 0.6 0.5 0.4 0.3 0.2 0.1
SPEC1 Ta=25 Ta=85 Ta=-40
Fig.28 Internal write cycle timetWR 0.6 0.5 tI(SDA H)[s]
Ta=25
Fig.29 Noise removal valid time tI(SCL H) 0.6 0.5 tI(SDA L)[s] 0.4
Ta=-40
tI(SCL L)[s]
0.4 0.3
Ta=-40 Ta=85
0.3 0.2
Ta=25 Ta=85 SPEC1
0.2
SPEC1,2
0.1 0 0 1 2 3 Vcc[V] 4 5 6 0 1 2 3 Vcc[V] 4 5 6
0.1 0 0 3 4 5 6 Vcc[V] Fig.32 Noise removal valid time tI(SDA L) 1 2
0
Fig.30 Noise removal valid time tI(SCL L) 0.2
SPEC1,2
Fig.31 Noise removal valid time tI(SDA H) 1.2 1
SPEC1,2
0 tSU:WP[s]
tHIGH:WP[s]
0.8 0.6 0.4 0.2 0
Ta=-40 Ta=25 Ta=85
-0.2
Ta=85
-0.4
Ta=25 Ta=-40
-0.6 0 1 2 3 Vcc[V] 4 5 6
0
1
2
3 Vcc[V]
4
5
6
Fig.33 WP setup timetSU:WP
Fig.34 WP valid timetHIGH:WP
6/32
2 I C BUS communication I2C BUS data communication I2C BUS data communication starts by start condition input, and ends by stop condition input. Data is always 8bit long, and acknowledge is always required after each byte. I2C BUS carries out data transmission with plural devices connected by 2 communication lines of serial data (SDA) and serial clock (SCL). Among devices, there are "master" that generates clock and control communication start and end, and "slave" that is controlled by address peculiar to devices. EEPROM becomes "slave". And the device that outputs data to bus during data communication is called "transmitter", and the device that receives data is called "receiver".
SDA
SCL
1-7 S START ADDRESS condition
8
9
1-7
8
9
1-7
8
9 P STOP condition
R/W
ACK
DATA
ACK
DATA
ACK
Fig.35 Data transfer timing
Start condition (Start bit recognition) Before executing each command, start condition (start bit) where SDA goes from 'HIGH' down to 'LOW' when SCL is 'HIGH' is necessary. This IC always detects whether SDA and SCL are in start condition (start bit) or not, therefore, unless this confdition is satisfied, any command is executed. Stop condition (stop bit recongnition) Each command can be ended by SDA rising from 'LOW' to 'HIGH' when stop condition (stop bit), namely, SCL is 'HIGH' Acknowledge (ACK) signal This acknowledge (ACK) signal is a software rule to show whether data transfer has been made normally or not. In master and slave, the device (-COM at slave address input of write command, read command, and this IC at data output of read command) at the transmitter (sending) side releases the bus after output of 8bit data. The device (this IC at slave address input of write command, read command, and -COM at data output of read command) at the receiver (receiving) side sets SDA 'LOW' during 9 clock cycles, and outputs acknowledge signal (ACK signal) showing that it has received the 8bit data. This IC, after recognizing start condition and slave address (8bit), outputs acknowledge signal (ACK signal) 'LOW'. Each write action outputs acknowledge signal (ACK signal) 'LOW', at receiving 8bit data (word address and write data). Each read action outputs 8bit data (read data), and detects acknowledge signal (ACK signal) 'LOW'. When acknowledge signal (ACK signal) is detected, and stop condition is not sent from the master (-COM) side, this IC continues data output. When acknowledge signal (ACK signal) is not detected, this IC stops data transfer, and recognizes stop cindition (stop bit), and ends read action. And this IC gets in status.
Device addressing Output slave address after start condition from master. The significant 4 bits of slave address are used for recognizing a device type. The device code of this IC is fixed to '1010'. Next slave addresses (A2 A1 A0 --- device address) are for selecting devices, and plural ones can be used on a same bus according to the number of device addresses. The most insignificant bit (R/W --- READ / WRITE) of slave address is used for designating write or read action, and is as shown below. Setting R / W to 0 ------- write (setting 0 to word address setting of random read) Setting R / W to 1 ------- read
Type BR24L01A-W 101 BR24L02-W 101 BR24L04-W 101 BR24L08-W 101 BR24L16-W 101 BR24L32-W 101 BR24L64-W 101 PS, P0P2 are page select bits. Note) 0 0 0 0 0 0 0 Slave address A2 A2 A2 A2 P2 A2 A2 A1 A1 A1 P1 P1 A1 A1 A0 A0 PS P0 P0 A0 A0 R/W R/W R/W R/W R/W R/W R/W Maximum number of connected buses 8 8 4 2 1 8 8 A0 A1 A2 GND 1 2 3 4 BR24L01A-W BR24L02-W BR24L04-W BR24L08-W BR24L16-W BR24L32-W BR24L64-W 8 7 6 5 Vcc WP SCL SDA
Up to 4 units BR24L04-W, up to 2 units of BR24L08-W, and one unit of BR24L16-W can be connected. Device address is set by 'H' and 'L' of each pin of A0, A1, and A2.
7/32
Write Command Write cycle
Arbitrary data is written to EEPROM. When to write only 1 byte, byte write is normally used, and when to write continuous data of 2 bytes or more, simultaneous write is possible by page write cycle. The maximum number of write bytes is specified per device of each capacity. Up to 32 arbitrary bytes can be written. (In the case of BR24L32 / L64-W)
S T A R T SDA LINE W R I T E WA 7 R A *1 /C WK S T O P D0 A C K
SLAVE ADDRESS 1 0 1 0 A2 A1 A0
WORD ADDRESS WA 0 A C K D7
DATA
Note)
*1 As for WA7, BR24L01A-W becomes Don't care.
Fig.36 Byte write cycle
S T A R T SDA LINE W R I T E
(BR24L01A/02/04/08/16-W)
S T O P D0 A C K
SLAVE ADDRESS 1 0 1 0 A2 A1 A0
1st WORD ADDRESS
WAWA 12 11
2nd WORD ADDRESS
WA 0
DATA
*
*
*
D7 A C K
Note)
RA /C WK
*1
A C K
*1 As for WA12, BR24L32-W becomes Don't care.
Fig.37 Byte write cycle
S T A R T SDA L IN E W R I T E WA 7 RA / C *1 WK
(BR24L32/64-W)
S T O P
SLAVE ADDRESS 1 0 1 0 A 2A 1A 0
W ORD A D D R E S S (n ) WA 0 A C K D7
D A TA (n ) D0 A C K
D A TA (n +1 5 )
*2
D0 A C K
*1 As for WA7, BR24L01A-W becomes Don't care. *2 As for BR24L01A/02-W becomes (n+7).
N o te )
Fig.38 Page write cycle
S T A R T SDA L IN E W R I T E
*
(BR24L01A/02/04/08/16-W)
S T O P
SLAVE ADDRESS 1 0 1 0 A 2A 1A 0
1 st W O R D A D D R E S S (n )
WA WA 1 2 11
2nd W ORD A D D R E S S (n )
WA 0
D A T A (n ) D7 A C K D0 A C K
D A TA (n + 3 1 ) D0 A C K
*
*
N ote )
RA /C WK
*1
A C K
*1 As for WA12, BR24L32-W becomes Don't care.
Fig.39 Page write cycle
(BR24L32/64-W)
Data is written to the address designated by word address (n-th address) By issuing stop bit after 8bit data input, write to memory cell inside starts. When internal write is started, command is not accepted for tWR (5ms at maximum). By page write cycle, the following can be written in bulk : Up to 8 bytes ( BR24L01A-W, BR24L02-W : Up to 16bytes (BR24L04-W, BR24L08-WBR24L16-W : Up to 32bytes (BR24L32-W, BR24L64-W And when data of the maximum bytes or higher is sent, data from the first byte is overwritten. (Refer to "Internal address increment" of "Notes on page write cycle" in P9/32.) As for page write cycle of BR24L01A-W and BR24L02-W, after the significant 5 bits (4 significant bits in BR24L01-W) of word address are designated arbitrarily, and as for page write command of BR24L04-W, BR24L08-W, and BR24L16-W, after page select bit (PS) of slave address is designated arbitrarily, by continuing data input of 2 bytes or more, the address of insignificant 4 bits (insignificant 3 bit in BR24L01A-W, and BR24L02-W) is incremented internally, and data up to 16 bytes (up to 8 bytes in BR24L01A-W and BR24L02-W) can be written. As for page write cycle of BR24L32-W and BR24L64-W, after the significant 7 bits (in the case of BR24L32-W) of word address, or the significant 8 bits (in the case of BR24L64-W) of word address are designated arbitrarily, by continuing data input of 2 byte or more, the address of insignificant 5 bits is incremented internally, and data up to 32 bytes can be written. Note)
*1 *2 *3
1 0 1 0 A 2A 1 0 A
*1 *2 *3
In BR24L16-W, A2 becomes P2. In BR24L08-W, BR24L16-W, A1 becomes P1. In BR24L04-W, A0 becomes PS, and in BR24L08-W and BR24L16-W, A0 becomes P0.
Fig.40 Difference of slave address of each type
8/32
Notes on write cycle continuous input
At STOP (stop bit), write starts.
S T A R T SDA LINE
SLAVE ADDRESS
W R I T E
WORD ADDRESS
*1 WA 7 WA 0
DATA(n)
DATA(n+7)*3
*2
S T O P
S T A R T
10 10
1 0 1 0 A2A1A0
D7
D0
D0
Note)
RA /C WK
A C K
A C K
A C K
Next command
tWR(maximum : 5ms) Command is not accepted for this period.
*1
BR24L01A-W becomes Don't care. BR24L04-W, BR24L08-W, and BR24L16-W become (n+15). BR24L32-W and BR24L64-W become (n+31).
Fig.41 Page write cycle
*2 *3
Note)
*1 *2 *3
*1 *2 *3
In BR24L16-W, A2 becomes P2. In BR24L08-W, BR24L16-W, A1 becomes P1. In BR24L04-W, A0 becomes PS, and in BR24L08-W and in BR24L16-W, A0 becomes P0.
1 0 1 0 A 2A 1 0 A
Fig.42 Difference of each type of slave address Notes on page write cycle List of numbers of page write
Number of Pages Product number 8Byte BR24L01A-W BR24L02-W 16Byte BR24L04-W BR24L08-W BR24L16-W 32Byte BR24L32-W BR24L64-W WA7 ----0 ----0 ----0 ------------WA4 0 0 0 WA3 0 0 0 --------WA2 0 0 0 WA1 0 0 1 WA0 0 1 0 Increment
Internal address increment Page write mode (in the case of BR24L02-W)
---------
The above numbers are maximum bytes for respective types. Any bytes below these can be written.
06h
0 0 0
-------------
0 0 0
0 0 0
1 1 0
1 1 0
0 1 0
In the case BR24L02-W, 1 page=8bytes, but the page write cycle write time is 5ms at maximum for 8byte bulk write. It does not stand 5ms at maximum x 8byte=40ms(Max.).
Significant bit is fixed. No digit up For example, when it is started from address 06h, therefore, increment is made as below, 06h 07h 00h 01h ---, which please note.
06h06 in hexadecimal, therefore, 00000110 becomes a binary number.
Write protect (WP) terminal Write protect (WP) function When WP terminal is set Vcc (H level), data rewrite of all addresses is prohibited. When it is set GND (L level), data rewrite of all address is enabled. Be sure to connect this terminal to Vcc or GND, or control it to H level or L level. Do not use it open. At extremely low voltage at power ON / OFF, by setting the WP terminal 'H', mistake write can be prevented. During tWR, set the WP terminal always to 'L'. If it is set 'H', write is forcibly terminated.
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Read Command Read cycle Data of EEPROM is read. In read cycle, there are random read cycle and current read cycle. Random read cycle is a command to read data by designating address, and is used generally. Current read cycle is a command to read data of internal address register without designating address, and is used when to verify just after write cycle. In both the read cycles, sequential read cycle is available, and the next address data can be read in succession.
S T A R T SDA L IN E W R I T E WA 7 R A *1 /C WK S T A R T R E A D D7 RA /C WK S T O P D0 A C K
It is necessary to input 'H' to the last ACK.
SLAVE ADDRESS 1 0 1 0 A 2 A 1A 0 N o te )
W ORD A D D R E S S (n ) WA 0 A C K
SLAVE ADDRESS 1 0 1 0 A 2 A 1A 0
D A TA (n )
Fig.43 Random read cycle (BR24L01A/02/04/08/16-W)
S T A R T SDA LINE W R I T E S T A R T R E A D S T O P
*1 As for WA7, BR24L01A-W become Don't care.
SLAVE ADDRESS
1st WORD ADDRESS
2nd WORD ADDRESS
WA 0
SLAVE ADDRESS
DATA(n)
1 0 1 0 A2A1A0
*** RA /C WK
WAWA 12 11
1 0 1 0 A2 A1A0
D7
D0
Note)
*1
A C K
A C K
RA /C WK
A C K
Fig.44 Random read cycle (BR24L32/64 -W)
S T A R T SDA L IN E R E A D D7 RA /C WK S T O P D0 A C K
*1 As for WA12, BR24L32-W become Don't care.
S LA V E ADDRESS 1 0 1 0 A 2 A 1A 0
D A TA (n )
It is necessary to input 'H' to the last ACK.
N o te)
Fig.45 Current read cycle
S T A R T SDA LINE SLAVE ADDRESS R E A D S T O P D0 A C K
DATA(n)
DATA(n+x)
1 0 1 0 A2 A1A0 RA /C WK
D7
D0 A C K A C K
D7
Note
Fig.46 Sequential read cycle (in the case of current read cycle) In random read cycle, data of designated word address can be read. When the command just before current read cycle is random read cycle, current read cycle (each including sequential read cycle), data of incremented last read address (n)-th address, i.e., data of the (n+1)-th address is output. When ACK signal 'LOW' after D0 is detected, and stop condition is not sent from master (-COM) side, the next address data can be read in succession. Read cycle is ended by stop condition where 'H' is input to ACK signal after D0 and SDA signal is started at SCL signal 'H' . When 'H' is not input to ACK signal after D0, sequential read gets in, and the next data is output. Therefore, read command cycle cannot be ended. When to end read command cycle, be sure input stop condition to input 'H' to ACK signal after D0, and to start SDA at SCL signal 'H'. Sequential read is ended by stop condition where 'H' is input to ACK signal after arbitrary D0 and SDA is started at SCL signal 'H'. Note)
*1 *2 *3
*1 *2 *3
In BR24L16-W, A2 becomes P2. In BR24L08-W, BR24L16-W, A1 becomes P1. In BR24L04-W, A0 becomes PS, and in BR24L08-W and BR24L16-W, A0 becomes P0.
1 0 1 0 A 2A 1 0 A
Fig.47 Difference of slave address of each type
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Software reset Software reset is executed when to avoid malfunction after power on, and to reset during command input. Software reset has several kinds, and 3 kinds of them are shown in the figure below. (Refer to Fig.48(a), Fig.48(b), and Fig.48(c).) In dummy clock input area, release the SDA bus ('H' by pull up). In dummy clock area, ACK output and read data '0' (both 'L' level) may be output from EEPROM, therefore, if 'H' is input forcibly, output may conflict and over current may flow, leading to instantaneous power failure of system power source or influence upon devices.
Dummy clockx14 Startx2
SCL SDA
1
2
13
14
Normal command Normal command
Fig.48-(a) The case of dummy clock +START+START+ command input
Start Dummy clockx9 Start
SCL SDA
1
2
8
9
Normal command Normal command
Fig.48-(b) The case of START +9 dummy clocks +START+ command input
Startx9
SCL SDA
1
2
3
7
8
9
Normal command Normal command
Fig.48-(c) STARTx9+ command input
Start command from START input.
Acknowledge polling During internal write execution, all input commands are ignored, therefore ACK is not sent back. During internal automatic write execution after write cycle input, next command (slave address) is sent, and if the first ACK signal sends back 'L', then it means end of write action, while if it sends back 'H', it means now in writing. By use of acknowledge polling, next command can be executed without waiting for tWR = 5ms. When to write continuously, R/W = 0, when to carry out current read cycle after write, slave address R/W = 1 is sent, and if ACK signal sends back 'L', then execute word address input and data output and so forth.
First write command
S T A R T S T O P S T Slave A R address T A C K H
During internal write, ACK = HIGH is sent back. S T Slave A R address T A C K H
Write command
tWR Second write command
S T Slave A R address T A C K H S T Slave A R address T A C Word K address L A C K L A C K L S T O P
...
Data
tWR
After completion of internal write, ACK=LOW is sent back, so input next word address and data in succession.
Fig.49 Case to continuously write by acknowledge polling
11/32
WP valid timing (write cancel) WP is usually fixed to 'H' or 'L', but when WP is used to cancel write cycle and so forth, pay attention to the following WP valid timing. During write cycle execution, in cancel valid area, by setting WP='H', write cycle can be cancelled. In both byte write cycle and page write cycle, the area from the first start condition of command to the rise of clock to taken in D0 of data(in page write cycle, the first byte data) is cancel invalid area. WP input in this area becomes Don't care. Set the setup time to rise of D0 taken SCL 100ns or more. The area from the rise of SCL to take in D0 to the end of internal automatic write (tWR) is cancel valid area. And, when it is set WP='H' during tWR, write is ended forcibly, data of address under access is not guaranteed, therefore, write it once again. (Refer to Fig.50.) After execution of forced end by WP, standby status gets in, so there is no need to wait for tWR (5ms at maximum).
Rise of D0 taken clock SCL SCL SDA D1 D0 SDA Rise of SDA
ACK
D0
ACK
Enlarged view S T Slave A address R T
Enlarged view
SDA
A C Word K address L
A C K D7 D6 D5 D4 D3 D2 D1 D0 L
A C K L
Data
A C K L
S T O P
tWR
WP cancel invalid area
WP cancel valid area
Write forced end
WP
Data is not written. Data not guaranteed
Fig.50 WP valid timing Command cancel by start condition and stop condition During command input, by continuously inputting start condition and stop condition, command can be cancelled. (Refer to Fig. 51.) However, in ACK output area and during data read, SDA bus may output 'L', and in this case, start condition and stop condition cannot be input, so reset is not available. Therefore, execute software reset. And when command is cancelled by start, stop condition, during random read cycle, sequential read cycle, or current read cycle, internal setting address is not determined, therefore, it is not possible to carry out current read cycle in succession. When to carry out read cycle in succession, carry out random read cycle.
SCL
SDA
1
0
1
0 Start condition Stop condition
Fig.51 Case of cancel by start, stop condition during slave address input
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I/O peripheral circuit Pull up resistance of SDA terminal SDA is NMOS open drain, so requires pull up resistance. As for this resistance value (RPU), select an appropriate value to this resistance value from microcontroller VIL, IL, and VOL-IOL characteristics of this IC. If RPU is large, action frequency is limited. The smaller the RPU, the larger the consumption current at action. Maximum value of RPU The maximum value of RPU is determined by the following factors. (1)SDA rise time to be determined by the capacitance (CBUS) of bus line of RPU and SDA should be tR or below. And AC timing should be satisfied even when SDA rise time is late. (2)The bus electric potential A to be determined by input leak total (IL) of device connected to bus at output of 'H' to SDA bus and RPU should sufficiently secure the input 'H' level (VIH) of microcontroller and EEPROM including recommended noise margin 0.2Vcc. Vcc - ILRPU 0.2Vcc VIH RPU 0.8VccVIH IL
RPU
Microcontroller
BR24LXX
Ex. ) When VCC =3V, IL=10A, VIH=0.7 VCC, from (2) RPU 0.8x30.7x3 10x10
-6
A
SDA terminal
IL
CBUS CBUS
IL
capacity
Bus line
300 [k] Minimum value of RPU The minimum value of RPU is determined by the following factors. (1)When IC outputs LOW, it should be satisfied that VOLMAX=0.4V and IOLMAX=3mA. VCCVOL RPU IOL RPU VCVOL IOL
Fig.52 I/O circuit diagram
(2)VOLMAX=0.4V should secure the input 'L' level (VIL) of microcontroller and EEPROM including recommended noise margin 0.1Vcc. VOLMAX VIL0.1 VCC Ex. ) When VCC =3V, VOL=0.4V, IOL=3mA, microcontroller, EEPROM VIL=0.3Vcc from (1) RPU And VOL = 0.4 [V] VIL = 0.3x3 = 0.9 [V] Pull up resistance of SCL terminal When SCL control is made at CMOS output port, there is no need, but in the case there is timing where SCL becomes 'Hi-Z', add a pull up resistance. As for the pull up resistance, one of several k ~ several ten k is recommended in consideration of drive performance of output port of microcontroller. A0, A1, A2, WP process Process of device address terminals (A0,A1,A2) Check whether the set device address coincides with device address input sent from the master side or not, and select one among plural devices connected to a same bus. Connect this terminal to pull up or pull down, or Vcc or GND. And, pins (N, C, PIN) not used as device address may be set to any of 'H' , 'L', and 'Hi-Z'. Types with N.C.PIN BR24L16/F/FJ/FV/FVT/FVM/FVJ-W BR24L08/F/FJ/FV/FVT/FVM/FVJ/NUX-W BR24L04/F/FJ/FV/FVT/FVM/FVJ/NUX-W Process of WP terminal WP terminal is the terminal that prohibits and permits write in hardware manner. In 'H' status, only READ is available and WRITE of all address is prohibited. In the case of 'L', both are available. In the case of use it as an ROM, it is recommended to connect it to pull up or Vcc. In the case to use both READ and WRITE, control WP terminal or connect it to pull down or GND. A0, A1, A2 A0, A1 A0 Therefore, the condition (2) is satisfied. 30.4 3x10 867 []
-3
13/32
Cautions on microcontroller connection Rs 2 In I C BUS, it is recommended that SDA port is of open drain input/output. However, when to use CMOS input / output of tri state to SDA port, insert a series resistance Rs between the pull up resistance Rpu and the SDA terminal of EEPROM. This is controls over current that occurs when PMOS of the microcontroller and NMOS of EEPROM are turned ON simultaneously. Rs also plays the role of protection of SDA terminal against surge. Therefore, even when SDA port is open drain input/output, Rs can be used.
ACK
RPU
SCL RS SDA
'H' output of microcontroller 'L' output of EEPROM
Microcontroller
EEPROM
Over current flows to SDA line by 'H' output of microcontroller and 'L' output of EEPROM.
Fig.53 I/O circuit diagram
Fig.54 Input / output collision timing
Maximum value of Rs The maximum value of Rs is determined by the following relations. (1)SDA rise time to be determined by the capacity (CBUS) of bus line of Rpu and SDA should be tR or below. And AC timing should be satisfied even when SDA rise time is late. (2)The bus electric potential A to be determined by Rpu and Rs the moment when EEPROM outputs 'L' to SDA bus should sufficiently secure the input 'L' level (VIL) of microcontroller including recommended noise margin 0.1Vcc.
VCC RPU A RS IOL
Bus line capacity CBUS
(VCCVOL)xRS RPU+RS
VOL
+ VOL+0.1VCCVIL
RS
VILVOL0.1VCC 1.1VCCVIL
x
RPU
ExampleWhen VCC=3V,VIL=0.3VCC,VOL=0.4V,RPU=20k,
EEPROM
VIL
Microcontroller
*4
from(2),
RS
0.3x30.40.1x3 x 1.1x30.3x3
20x10
3
Fig.55 I/O circuit diagram
1.67k
Minimum value of Rs The minimum value of Rs is determined by over current at bus collision. When over current flows, noises in power source line, and instantaneous power failure of power source may occur. When allowable over current is defined as I, the following relation must be satisfied. Determine the allowable current in consideration of impedance of power source line in set and so forth. Set the over current to EEPROM 10mA or below.
VCC RS
'L' output
I VCC I
RPU RS
RS
Over current 'H' output
ExampleWhen VCC=3V, I=10mA RS 3 -3 10x10
Microcontroller
EEPROM
Fig.56 I/O circuit diagram
300
14/32
2 I C BUS input / output circuit Input (A0,A2,SCL)
Fig.57 Input pin circuit diagram Input / output (SDA)
Fig.58 Input / output pin circuit diagram
Input (A1, WP)
Fig.59 Input pin circuit diagram
Notes on power ON At power on, in IC internal circuit and set, Vcc rises through unstable low voltage area, and IC inside is not completely reset, and malfunction may occur. To prevent this, functions of POR circuit and LVCC circuit are equipped. To assure the action, observe the following conditions at power on. 1. Set SDA = 'H' and SCL ='L' or 'H' 2. Start power source so as to satisfy the recommended conditions of tR, tOFF, and Vbot for operating POR circuit.
VCC tR
Recommended conditions of tR, tOFF,Vbot
tR
tOFF Vbot
tOFF
Vbot
10ms or below 10ms or longer 0.3V or below 100ms or below 10ms or longer 0.2V or below
0
Fig.60 Rise waveform diagram
15/32
3. Set SDA and SCL so as not to become 'Hi-Z'. When the above conditions 1 and 2 cannot be observed, take the following countermeasures. a) In the case when the above condition 1 cannot be observed. When SDA becomes 'L' at power on . Control SCL and SDA as shown below, to make SCL and SDA, 'H' and 'H'.
VCC SCL
tLOW
SDA
After Vcc becomes stable After Vcc becomes stable
tDH
tSU:DAT
tSU:DAT
Fig.61 When SCL= 'H' and SDA= 'L'
Fig.62 When SCL='L' and SDA='L'
b) In the case when the above condition 2 cannot be observed. After power source becomes stable, execute software reset(P11). c) In the case when the above conditions 1 and 2 cannot be observed. Carry out a), and then carry out b). Low voltage malfunction prevention function LVCC circuit prevents data rewrite action at low power, and prevents wrong write. At LVCC voltage (Typ. =1.2V) or below, it prevent data rewrite. Vcc noise countermeasures Bypass capacitor When noise or surge gets in the power source line, malfunction may occur, therefore, for removing these, it is recommended to attach a by pass capacitor (0.1F) between IC Vcc and GND. At that moment, attach it as close to IC as possible. And, it is also recommended to attach a bypass capacitor between board Vcc and GND.
Cautions on use (1)Described numeric values and data are design representative values, and the values are not guaranteed. (2)We believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further sufficiently. In the case of use by changing the fixed number of external parts, make your decision with sufficient margin in consideration of static characteristics and transition characteristics and fluctuations of external parts and our LSI. (3)Absolute maximum ratings If the absolute maximum ratings such as impressed voltage and action temperature range and so forth are exceeded, LSI may be destructed. Do not impress voltage and temperature exceeding the absolute maximum ratings. In the case of fear exceeding the absolute maximum ratings, take physical safety countermeasures such as fuses, and see to it that conditions exceeding the absolute maximum ratings should not be impressed to LSI. (4)GND electric potential Set the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltage is lower than that of GND terminal. (5)Terminal design In consideration of permissible loss in actual use condition, carry out heat design with sufficient margin. (6)Terminal to terminal shortcircuit and wrong packaging When to package LSI onto a board, pay sufficient attention to LSI direction and displacement. Wrong packaging may destruct LSI. And in the case of shortcircuit between LSI terminals and terminals and power source, terminal and GND owing to foreign matter, LSI may be destructed. (7)Use in a strong electromagnetic field may cause malfunction, therefore, evaluate design sufficiently.
16/32
I2C BUS Serial EEPROMs
BR24S-W Series BR24S16-W, BR24S32-W, BR24S64-W, BR24S128-W, BR24S256-W
Description 2 BR24S-W series is a serial EEPROM of I C BUS interface method. Features 2 Completely conforming to the world standard I C BUS. All controls available by 2 ports of serial clock (SCL) and serial data (SDA) Other devices than EEPROM can be connected to the same port, saving microcontroller port. 1.75.5V single power source action most suitable for battery use. FAST MODE 400kHz at 1.75.5V Page write mode useful for initial value write at factory shipment. Highly reliable connection by Au pad and Au wire. Auto erase and auto end function at data rewrite. Low current consumption At write operation (5V) : 0.5mA (Typ.) At read operation (5V) : 0.2mA (Typ.) At standby operation (5V) : 0.1A (Typ.) Write mistake prevention function Write (write protect) function added Write mistake prevention function at low voltage SOP8/SOP-J8/SSOP-B8/TSSOP-B8/MSOP8/TSSOP-B8J/VSON008X2030 compact package Data rewrite up to 1,000,000 times Data kept for 40 years Noise filter built in SCL / SDA terminal Shipment data all address FFh Page write Number of pages Product number
16Byte BR24S16-W
32Byte BR24S32-W BR24S64-W
64Byte BR24S128-W BR24S256-W
BR24S series
Capacity 16Kbit 32Kbit 64Kbit 128Kbit 256Kbit Bit format 2Kx8 4Kx8 8Kx8 16Kx8 32Kx8 Type BR24S16-W BR24S32-W BR24S64-W BR24S128-W BR24S256-W Power source voltage 1.75.5V 1.75.5V 1.75.5V 1.75.5V 1.75.5V SOP8 F SOP-J8 FJ SSOP-B8 TSSOP-B8 FV FVT MSOP8 FVM TSSOP-B8J FVJ VSON008 X2030 NUX
17/32
Absolute maximum ratings (Ta=25)
Parameter Impressed voltage Symbol Vcc Limits Unit V
*1 *2 *3 *4 *5 *6
Memory cell characteristics (Ta=25,Vcc=1.7V~5.5V)
Parameter Number of data rewrite Limits Min. 1,000,000 40 Typ. Max. Unit Times Years
0.3+6.5
450(SOP8) 450(SOP-J8) 300(SSOP-B8)
Permissible dissipation
Pd
330(TSSOP-B8) 310(MSOP8) 310(TSSOP-B8J)
mW
times
*1 : Not 100% TESTED
*1 *1

Data hold years
300(VSON008X2030) *7 Storage temperature range Action temperature range Terminal Voltage Tstg Topr
Recommended operating condition

V
65 +125 40 +85 0.3Vcc1.0
Parameter Power source voltage Input voltage
Symbol Vcc VIN
Limits 1.75.5 0Vcc
Unit V
* When using at Ta=25 or higher, 4.5mW(*1,*2) 3.0mW(*3,*7) 3.3mW(*4) 3.1mW(*5,*6) to be reduced per 1
Electrical characteristics
(Unless otherwise specified, Ta=40+85, Vcc=1.75.5V)
Limits Parameter "H" Input Voltage1 "L" Input Voltage1 "L" Output Voltage1 "L" Output Voltage2 Input Leakage Current Output Leakage Current Symbol Min VIH1 VIL1 VOL1 VOL2 ILI ILO 0.7Vcc 0.3 Typ. Max. Vcc+1.0 0.3Vcc 0.4 0.2 1 1 V V V V A A IOL=3.0mA , 2.5VVcc5.5V (SDA) IOL=0.7mA , 1.7VVcc2.5V (SDA) VIN=0Vcc VOUT=0Vcc (SDA) Vcc=5.5V , fSCL =400kHz, tWR=5ms Current consumption at action ICC1 2.5 2.0 mA Byte Write, Page Write BR24S16/32/64-W Vcc=5.5V , fSCL =400kHz, tWR=5ms Byte Write, Page Write BR24S128/256-W Vcc=5.5V , fSCL =400kHz ICC2 Standby Current ISB 0.5 2.0 mA A Random read, Current read, Sequential read Vcc=5.5V , SDASCL=Vcc A0, A1, A2=GND, WP=GND Unit Condition
Action iming characteristics
(Unless otherwise specified, Ta=40+85, Vcc=1.75.5V)
Parameter
SCL Frequency Data clock "High" time Data clock "Low" time
Symbol
fSCL tHIGH tLOW
Limits Min.
0.6 1.2 0.6 0.6 0 100 0.1 0.1 0.6 1.2 0 0.1 1.0
Typ.

Max.
400 0.3 0.3 0.9 5 0.1
Unit
kHz s s s s s s ns ns s s s s ms s ns s s

1 1
SDA, SCL rise time SDA, SCL fall time
*1 *1
tR tF tHD:STA tSU:STA tHD:DAT tSU:DAT tPD tDH tSU:STO tBUF tWR tI tHD:WP tSU:WP tHIGH:WP
Start condition hold time Start condition setup time Input data hold time Input data setup time Output data delay time Output data hold time Stop condition data setup time Bus release time before transfer start Internal write cycle time Noise removal valid period (SDA,SCL terminal) WP hold time WP setup time WP valid time
Radiation resistance design is not made.
*1 : Not 100% TESTED
Sync data input/output timing
tR SCL tHD:STA SDA () (Input) tBUF SDA () (Output) tPD tDH tSU:DAT tLOW tHD:DAT tF tHIGH
SCL DATA(1) SDA D1 D0 ACK DATA(n) ACK WR WP
Stop condition
Input read at the rise edge of SCL Data output in sync with the fall of SCL
tSUWP
HDWP
Fig.1-(a) Sync data input / output timing
SCL tSU:STA
SDA
Fig.1-(d) WP timing at write execution
SCL
tHD:STA tSU:STO
DATA(1) SDA D1 D0 ACK
DATA(n) ACK tHIGH:WP
tWR tWR
Fig.1-(b) Start - stop bit timing
START BIT
STOP BIT
WP
SCL
SDA
D0 ACK WRITE DATA(n) STOP CONDITION
tWR START CONDITION
At write execution, in the area from the D0 taken clock rise of the first DATA(1), to tWR, set WP= 'LOW'. By setting WP "HIGH" in the area, write can be cancelled. When it is set WP = 'HIGH' during tWR, write is forcibly ended, and data of address under access is not guaranteed, therefore write it once again.
Fig.1-(c) Write cycle timing
Fig.1-(e) WP timing at write cancel
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Block diagram
*2
A0
1
*1 11bit 12bit 13bit 14bit 15bit
16Kbit256Kbit EEPROM array 8bit
*1 11bit
12bit 13bit 14bit 15bit
8
Vcc
*2
A1
2
Adddress decoder
Slave - word address register
Data register
7
WP
START
*2
STOP
A2
3
Control circuit ACK
6
SCL
GND
4
High voltage generating circuit
Power source voltage detection
5
SDA
1
11bit: BR24S16-W 12bit: BR24S32-W 13bit: BR24S64-W 14bit: BR24S128-W 15bit: BR24S256-W
2
A0, A1, A2= Don't use: BR24S16-W
Fig.2 Block
diagram
Pin assignment and description
A0
1
8
Vcc
Terminal name A0 A1 A2 GND SDA
Input/ Output Input Input Input Input / Output Input Input BR24S16-W Don't use Don't use Don't use
Function BR24S32/64/128/256-W Slave address setting Slave address setting Slave address setting
A1
2
A2
3
BR24S16-W BR24S32-W BR24S64-W BR24S128-W BR24S256-W
7
WP
6
SCL
Reference voltage of all input / output, 0V. Slave and word address, Serial data input serial data output Serial clock input Write protect terminal Connect the power source.
GND
4
5
SDA
SCL WP Vcc
Characteristic data (The following values are Typ. ones.)
6 H INPUT VOLTAGE : VIH[V] L INPUT VOLTAGE : VIL[V] 5 4 3 6
1 L OUTPUT VOLTAGE : VOL[V]
Ta=-40 Ta=25 Ta=85
5 4 3 2 1
Ta=-40 Ta=25 Ta=85
0.8 0.6 0.4
Ta=-40 Ta=25 Ta=85
SPEC
2 1 0 0 1 2 3 4 5 SUPPLY VOLTAGE : Vcc[V] 6
SPEC
0.2 0 0 1 2 3 4 5 6 7 L OUTPUT CURRENT : IOL[mA] 8
SPEC
0 0 1 2 3 4 5 SUPPLY VOLTAGE : Vcc[V] 6
Fig.3'H' input voltage VIH (A0,A1,A2,SCL,SDA,WP)
1 INPUT LEAK CURRENT : ILI[uA] L OUTPUT VOLTAGE : VOL[V] 0.8 0.6 0.4 0.2 0 0 1 2 3 4 5 L OUTPUT CURRENT : IOL[mA] 6 1.2 1 0.8 0.6 0.4 0.2 0 0 1
Fig.4'L' input voltage VIL (A0,A1,A2,SCL,SDA,WP)
1.2
Fig.5 'L' output voltage VOL-IOL(Vcc=1.7V)
OUTPUT LEAK CURRENT : ILO[uA]
SPEC
1 0.8 0.6 0.4 0.2 0
SPEC
Ta=-40 Ta=25 Ta=85
SPEC
Ta=-40 Ta=25 Ta=85
Ta=-40 Ta=25 Ta=85
2
3
4
5
6
0
1
SUPPLYVOLTAGE : Vcc[V]
2 3 4 5 SUPPLY VOLTAGE : Vcc[V]
6
Fig.6'L' output voltage VOL-IOL(Vcc=2.5V)
Fig.7Input leak current ILI (A0,A,A2,SCL,WP)
Fig.8Output leak current ILO(SDA)
19/32
Characteristic data (The following values are Typ. ones.)
2.5
3.5
0.6
SPEC
2 CURRENT CONSUMPTION AT WRITING : Icc1[mA]
3 CURRENT CONSUMPTION AT WRITING : Icc1[mA] 2.5 2 1.5 1 0.5 0 CURRENT CONSUMPTION AT READING : Icc2[mA]
SPEC SPEC
0.5 0.4 0.3 0.2 0.1 0 0 1 2 3 4 5 6 0 1 2 3 4 5 6 SUPPLY VOLTAGE : Vcc[V] SUPPLY VOLTAGE : Vcc[V]
1.5
1
Ta=-40 Ta=25 Ta=85
Ta=-40 Ta=25 Ta=85
Ta=-40 Ta=25 Ta=85
0.5
0 0 1 2 3 4 5 6 SUPPLY VOLTAGE : Vcc[V]
Fig.9 Current consumption at WRITE operation ICC1 (fSCL=400kHz BR24S16/32/64-W)
2.5
Fig.10Current consumption at WRITE operation Icc1 (fSCL=400kHz BR24S128/256-W)
10000 SCL FREQUENCY : f[HZ]
Fig.11 Current consumption at READ operation ICC2 (fSCL=400kHz)
5
SPEC
STANBY CURRENT : ISB[uA] 2
SPEC
DATA CLK H TIME : tHIGH[uA]
1000
4
SPEC
100
1.5
3
1
0.5
Ta=-40 Ta=25 Ta=85
10
Ta=-40 Ta=25 Ta=85
2
Ta=-40 Ta=25 Ta=85
1
1
0 0 1 2 3 4 5 6 SUPPLY VOLTAGE : Vcc[V]
0.1 0 1 2 3 4 5 6 SUPPLY VOLTAGE : Vcc[V]
0 0 1 2 3 4 SUPPLY VOLTAGE : Vcc[V] 5 6
Fig.12Stanby operation ISB
START CONDITION HOLD TIME : tHD : STA[us] 5 5
Fig.13SCL frequency fSCL
5.9
Fig.14 Data clock High Period tHIGH
4
START CONDITION SET UP TIME : tSU:STA[uA]
SPEC
CLK L TIME : tLOW[us]
SPEC
4
4.9 3.9 2.9 1.9 0.9 -0.1
3
3
2
Ta=-40 Ta=25 Ta=85
2
Ta=-40 Ta=25 Ta=85
Ta=-40 Ta=25 Ta=85 SPEC
1
1
0 0 1 2 3 4 SUPPLY VOLTAGE : Vcc[V] 5 6
0 0 1 2 3 4 5 6 SUPPLY VOLTAGE : Vcc[V]
0
1
2 3 4 5 SUPPLY VOLTAGE : Vcc[V]
6
Fig.15 Data clock Low PeriodtLOW
Fig.16 Start Condition Hold Time tHD : STA
Fig.17Start Condition Setup TimetSU : STA
50
INPUT DATA HOLD TIME : tHD :DAT[ns]
INPUT DATA HOLD TIME : tHD: STA[ns]
50
300 INPUT DATA SET UP TIME : tSU: DAT[ns]
SPEC
0
SPEC
0
200
SPEC
100
-50
-50
-100
Ta=-40 Ta=25 Ta=85
-100
0
-150
-150
Ta=-40 Ta=25 Ta=85
-100
Ta=-40 Ta=25 Ta=85
-200 0 1 2 3 4 5 6
SUPPLY VOLTAGE : Vcc[V]
-200 0 1 2 3 4 5 6 SUPPLY VOLTAGE : Vcc[V]
-200 0 1 2 3 4 5 6 SUPPLY VOLTAGE : Vcc[V]
Fig.18Input Data Hold Time tHD : DATHIGH
Fig.19Input Data Hold Time HD : DAT(LOW
Fig.20Input Data Setup Time SU: DAT(HIGH)
300 INPUT DATA SET UP TIME : tSU : DAT[ns] OUTPUT DATA DELAY TIME : tPD[us]
4 OUTPUT DATA DELAY TIME : tPD[us]
4
200
3
Ta=-40 Ta=25 Ta=85 SPEC
3
SPEC
100
Ta=-40 Ta=25 Ta=85 SPEC
2
2
0
-100
Ta=-40 Ta=25 Ta=85
1
1
-200 0 1 2 3 4 5 6 SUPPLY VOLTAGE : Vcc[V]
0 0 1 2 3 4 5 6 SUPPLY VOLTAGE : Vcc[V]
0
0 1 2 3 4 5 6
SUPPLY VOLTAGE : Vcc[V]
Fig.21Input Data setup time tSU : DAT(LOW)
Fig.22'L' Data output delay time tPD0
Fig.23 'H' Data output delay time PD1
20/32
Characteristic data (The following values are Typ. ones.)
5 BUS OPEN TIME BEFORE TRANSMISSION : tBUF[us] INTERNAL WRITING CYCLE TIME : tWR[ms] 4 3 2 1 0 0 1 2 3 4 5 SUPPLY VOLTAGE : Vcc[V] 6
6
1
Ta=-40 Ta=25 Ta=85
5 4 3 2 1 0 0 1
SPEC
NOISE REDUCTION EFECTIVE TIME : tl(SCL H) [us]
SPEC
0.8 0.6 0.4 0.2 0
Ta=-40 Ta=25 Ta=85
SPEC
Ta=-40 Ta=25 Ta=85
2 3 4 5 SUPPLY VOLTAGE : Vcc[V] 6
0
1
2 3 4 5 SUPPLY VOLTAGE : Vcc[V]
6
Fig.24 BUS open time before transmissionBUF
0.6 NOISE REDUCTION EFECTIVE TIME : tl(SDA H)[us] NOISE REDUCTION EFECTIVE TIME : tl(SCL L)[us] 0.5 0.4 0.3 0.2 0.1 0 0 1 2 3 4 5 6 SUPPLY VOLTAGE : Vcc[V] 0.6
Fig.25 Internal writing cycle timeWR
Fig.26 Noise reduction efection time tlSCL H
0.6 NOISE REDUCTION EFFECTIVE TIME : tl(SAD L)[us]
Ta=-40 Ta=25 Ta=85
0.5 0.4 0.3 0.2
Ta=-40 Ta=25 Ta=85
0.5 0.4 0.3 0.2 0.1 0
SPEC
Ta=-40 Ta=25 Ta=85 SPEC
SPEC
0.1 0 0 2 4 6 SUPPLY VOLATGE : Vcc[V]
0
1
2
3
4
5
6
SUPPLY VOLTAGE : Vcc[V]
Fig.27Noise reduction efective timetlSCL L
Fig.28Noise resuction efecctive timeSDA H
Fig.29 Noise reduction efective time tlSDA L
0.2 WP SET UP TIME : tSU : WP[us] 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 0 1 2 3 4 5 SUPPLY VOLTAGE : Vcc[V] 6
1.2
SPEC
WP EFFECTIVE TIME : tHIGH : WP[us]
SPEC
1 0.8 0.6 0.4 0.2 0 0 1 2 3 4 5 SUPPLYVOLTAGE : Vcc[V] 6
Ta=-40 Ta=25 Ta=85
Ta=-40 Ta=25 Ta=85
Fig.30 WP setup time tSU : WP
Fig.31 WP efective time tHIGH : WP
21/32
I C BUS communication 2 I C BUS data communication 2 I C BUS data communication starts by start condition input, and ends by stop condition input. Data is always 8bit long, and acknowledge is always required after each byte. 2 I C BUS carries out data transmission with plural devices connected by 2 communication lines of serial data (SDA) and serial clock (SCL). Among devices, there are "master" that generates clock and control communication start and end, and "slave" that is controlled by addresses peculiar to devices. EEPROM becomes "slave". And the device that outputs data to bus during data communication is called "transmitter", and the device that receives data is called "receiver".
SDA
2
SCL
1-7 S START ADDRESS condition
8
9
1-7
8
9
1-7
8
9 P STOP condition
R/W
ACK
DATA
ACK
DATA
ACK
Fig.32 Data transfer timing Start condition (start bit recognition) Before executing each command, start condition (start bit) where SDA goes from 'HIGH' down to 'LOW' when SCL is 'HIGH' is necessary. This IC always detects whether SDA and SCL are in start condition (start bit) or not, therefore, unless this condition is satisfied, any command is executed. Stop condition (stop bit recognition) Each command can be ended by SDA rising from 'LOW' to 'HIGH' when stop condition (stop bit), namely, SCL is 'HIGH' Acknowledge (ACK) signal This acknowledge (ACK) signal is a software rule to show whether data transfer has been made normally or not. In master and slave, the device (-COM at slave address input of write command, read command, and this IC at data output of read command) at the transmitter (sending) side releases the bus after output of 8bit data. The device (this IC at slave address input of write command, read command, and -COM at data output of read command) at the receiver (receiving) side sets SDA 'LOW' during 9 clock cycles, and outputs acknowledge signal (ACK signal) showing that it has received the 8bit data. This IC, after recognizing start condition and slave address (8bit), outputs acknowledge signal (ACK signal) 'LOW'. Each write action outputs acknowledge signal) (ACK signal) 'LOW', at receiving 8bit data (word address and write data). Each read action outputs 8bit data (read data), and detects acknowledge signal (ACK signal) 'LOW'. When acknowledge signal (ACK signal) is detected, and stop condition is not sent from the master (-COM) side, this IC continues data output. When acknowledge signal (ACK signal) is not detected, this IC stops data transfer, and recognizes stop condition (stop bit), and ends read action. And this IC gets in standby status. Device addressing Output slave address after start condition from master. The significant 4 bits of slave address are used for recognizing a device type. The device code of this IC is fixed to '1010'. Next slave addresses (A2 A1 A0 --- device address) are for selecting devices, and plural ones can be used on a same bus according to the number of device addresses. The most insignificant bit (R/W --- READ/WRITE) of slave address is used for designating write or read action, and is as shown below. Setting R/W to 0 --- write (setting 0 to word address setting of random read) Setting R/W to 1 --- read
Type Slave address
Maximum number of connected buses
A0 1 A1 2
8
Vcc
BR24S16-W BR24S32-W,BR24S64-W, BR24S128-W,BR24S256-W
P0P2 are page select bits.
1010 1010
P2 A2
P1 A1
P0 A0
R/W R/W
1 8
A2
3
BR24S16-W BR24S32-W BR24S64-W BR24S128-W BR24S256-W
7
WP
6
SCL
GND
4
5
SDA
Note)Up to 1 units of BR24S16-W, and up to 8 units of BR24S32/64/128/256-W can be connected. Device address is set by 'H' and 'L' of each pin of A0, A1, and A2.
22/32
Write Command Write cycle Arbitrary data is written to EEPROM. When to write only 1 byte, byte write normally used, and when to write continuous data of 2 bytes or more, simultaneous write is possible by page write cycle. The maximum number of write bytes is specified per device of each capacity. Up to 64 arbitrary bytes can be written. (In the case of BR24S128/256-W)
S T A R T SDA LINE W R I T E WA 7 RA /C WK S T O P D0 A C K
SLAVE ADDRESS 1 0 1 0 A2 A1 A0
WORD ADDRESS WA 0 A C K D7
DATA
Note)
Fig.33 Byte write cycle (BR24S16-W)
S T A R T SDA LINE W R I T E S T O P D0 A C K
SLAVE ADDRESS 1 0 1 0 A2 A1 A0
1st WORD ADDRESS
WA WA WAWA 14 13 12 11
2nd WORD ADDRESS
WA 0
DATA
*1
D7 A C K
As for WA12, BR24S32-W becomes Don't care. As for WA13, BR24S32/64-W becomes Don't care. As for WA14, BR24S32/64/128-W becomes Don't care.
Note)
RA /C WK
*1
A C K
Fig.34 Byte write cycle (BR24S32/64/128/256-W)
S T A R T SDA L IN E W R I T E WA 7 RA / C *1 WK S T O P
SLAVE ADDRESS 1 0 1 0 A 2A 1A 0
W ORD A D D R E S S (n ) WA 0 A C K D7
D A T A (n ) D0 A C K
D A T A (n + 1 5 )
*2
D0 A C K
Note) )
Fig.35 Page write cycle
S T A R T SDA L IN E SLAVE ADDRESS 1 0 1 0 A 2A 1A 0 RA /C WK W R I T E
(BR24S16-W)
2nd W ORD A D D R E S S (n )
WA 0
1 st W O R D A D D R E S S (n )
W A W AW A W A 1 4 13 1 2 11
*2 D A T A (n ) D7 A C K D0 A C K D A TA (n + 3 1 ) D0 A C K
S T O P
*1
N o te )
*1
A C K
As for WA12, BR24S32-W becomes Don't care. As for WA13, BR24S32/64-W becomes Don't care. As for WA14, BR24S32/64/128-W becomes Don't care.
*2 As for BR24S128/256-W becomes (n+63).
Fig.36
Page write cycle (BR24S32/64/128/256-W)
Data is written to the address designated by word address (n-th address). By issuing stop bit after 8bit data input, write to memory cell inside starts. When internal write is started, command is not accepted for tWR (5ms at maximum). By page write cycle, the following can be written in bulk: Up to 16 bytes (BR24S16-W) : Up to 32 bytes (BR24S32-W, BR24S64-W) : Up to 64 bytes (BR24S128-W, BR24S256-W) And when data of the maximum bytes or higher is sent, data from the first byte is overwritten. (Refer to "Internal address increment of "Notes on page write cycle" in P24/32.) As for page write command of BR24S16-W, after page select bit(PS) of slave address is designated arbitrarily, by continuing data input of 2 bytes or more, the address of insignificant 4 bits is incremented internally, and data up to 16 bytes can be written. for page write cycle of BR24S32-W and BR24S64-W , after the significant 7 bits (in the case of BR24S32-W) of word address, As or the significant 8 bits (in the case of BR24S64-W) of word address are designated arbitrarily, by continuing data input of 2 bytes or more, the address of insignificant 5 bits is incremented internally, and data up to 32 bytes can be written. As for page write cycle of BR24S128-W and BR24S256-W, after the significant 9 bit (in the case of BR24S128-W) of word address, or the significant 10bit (in the case of BR24S256-W) of word address are designated arbitrarily, by continuing data input of 64 bytes or more. Note)
*1 *2 *3
1 0 1 0 A 2A 1 0 A
Fig.37
*1 In BR24S16-W, A2 becomes P2 *2 In BR24S16-W, A1 becomes P1 *3 In BR24S16-W, A0 becomes P0
Difference of slave address each type
23/32
Notes on write cycle continuous input
At STOP (stop bit) write starts.
S T A R T SDA LINE
SLAVE ADDRESS
W R I T E
WORD ADDRESS
WA 0
DATA(n)
DATA(n+15)
S T O P
S T A R T
1 0 10
1 0 1 0 P2 P1 P0
WA 7
D7
D0
D0
RA /C WK
A C K
A C K
A C K
Next command
tWR(maximum5ms) Command is not accepted for this period.
Fig.38
Page write cycle(BR24S16-W)
A t S TO P (stop bit) w rite starts.
SDA L IN E
S T A R T
SLAVE ADDRESS 1 0 1 0 A 2A 1A 0
W R I T E
1 st W O R D A D D R E S S (n )
W A W AW A W A 14 13 12 11
2nd W ORD A D D R E S S (n )
WA 0
D A T A (n ) D7 A C K D0 A C K
*2 D A TA (n+ 31 ) D0 A C K
S T O P
S T A R T 1010
*1
As for WA12, BR24S32-W becomes Don't care. As for WA13, BR24S32/64-W becomes Don't care. As for WA14, BR24S32/64/128-W becomes Don't care.
RA /C WK
*1
A C K
*2 As for BR24S128/256-W becomes (n+63).
N e xt co m m a n d tW R (ma ximu m : 5 m s) C o m m an d is n ot a ccep te d for th is period .
Fig.39
Page write cycle(BR24S32/64/128/256-W)
Notes on page write cycle
List of numbers of page write Number of pages Product number 16Byte BR24S16-W 32Byte BR24S32-W BR24S64-W 64Byte BR24S128-W BR24S256-W
Internal address increment Page write mode (in the case of BR24S16-W)
WA7 ----0 ----0 ----0 -------------
The above numbers are maximum bytes for respective types. Any bytes below these can be written.
In the case of BR24S256-W, 1 page = 64bytes, but the page write cycle write time is 5ms at maximum for 64byte bulk write. It does not stand 5ms at maximum x 64byte = 320ms(Max.).
WA4 0 0 0
WA3 0 0 0
WA2 WA1 0 0 0 0 0 1
---------
WA0 0 1 0
Increment
0Eh
0 0 0
-------------
0 0 0
1 1 0
1 1 0
1 1 0
0 1 0
Significant bit is fixed. No digit up
For example, when it is started from address 0Eh, therefore, increment is made as below, 0Eh0Fh00h01h, which please note. * 0Eh16 in hexadecimal, therefore, 00001110 becomes a binary number.
Write protect (WP) terminal Write protect (WP) function When WP terminal is set Vcc (H level), data rewrite of all address is prohibited. When it is set GND (L level), data rewrite of all address is enabled. Be sure to connect this terminal to Vcc or GND, or control it to H level or L level. Do not use it open. At extremely low voltage at power ON/OFF, by setting the WP terminal 'H', mistake write can be prevented. During tWR, set the WP terminal always to 'L'. If it is set 'H', write is forcibly terminated.
24/32
Read Command Read cycle Data of EEPROM is read. In read cycle, there are random read cycle and current read cycle. Random read cycle is a command to read data by designating address, and is used generally. Current read cycle is a command to read data of internal address register without designating address, and is used when to verify just after write cycle. In both the read cycles, sequential read cycle is available, and the next address data can be read in succession.
S T A R T SDA L IN E W R I T E WA 7 RA /C WK S T A R T R E A D D7 RA /C WK S T O P D0 A C K
SLAVE ADDRESS 1 0 1 0 A 2 A 1A 0
W ORD A D D R E S S (n) WA 0 A C K
S LA V E ADDRESS 1 0 1 0 A 2 A 1A 0
D A TA (n)
It is necessary to input 'H' to the last ACK.
N o te)
Fig.40 Random read cycle (BR24S16-W)
S T A R T SDA LINE W R I T E S T A R T R E A D S T O P
SLAVE ADDRESS
1st WORD ADDRESS
2nd WORD ADDRESS
WA 0
SLAVE ADDRESS
DATA(n)
1 0 1 0 A2A1A0
WA WA WAWA 14 13 12 11
1 0 1 0 A2A1A0
D7
D0
*1 As for WA12, BR24S32-W become Don't care. As for WA13, BR24S32/64-W become Don't care. As for WA14, R24S32/64/128-W become Don't care.
A C K
Note)
RA /C WK
*1
A C K
A C K
RA /C WK
Fig.41 Random read cycle (BR24S32/64/128/256-W)
S T A R T SDA L IN E
S LA V E ADDRESS 1 0 1 0 A 2 A 1A 0
R E A D D7 RA /C WK
D A TA (n ) D0 A C K
S T O P
It is necessary to input 'H' to the last ACK.
N ote )
Fig.42 Current read cycle
S T A R T SDA LINE R E A D S T O P D0 A C K
SLAVE ADDRESS
DATA(n)
DATA(n+x)
1 0 1 0 A2 A1A0 RA /C WK
D7
D0 A C K A C K
D7
Note
Fig.43 Sequential read cycle (in the case of current read cycle)
In random read cycle, data of designated word address can be read. When the command just before current read cycle is random read cycle, current read cycle (each including sequential read cycle), data of incremented last read address (n)-th address, i.e., data of the (n+1)-th address is output. When ACK signal 'LOW' after D0 is detected, and stop condition is not sent from master (-COM) side, the next address data can be read in succession. Read cycle is ended by stop condition where 'H' is input to ACK signal after D0 and SDA signal is started at SCL signal 'H'. When 'H' is not input to ACK signal after D0, sequential read gets in, and the next data is output. Therefore, read command cycle cannot be ended. When to end read command cycle, be sure input stop condition to input 'H' to ACK signal after D0, and to start SDA at SCL signal 'H'. Sequential read is ended by stop condition where 'H' is input to ACK signal after arbitrary D0 and SDA is started at SCL signal 'H'.
Vcc Note)
*1 *2 *3
1 0 1 0 A2 A1A0
Fig.44
*1 BR24S16-W A2 becomes P2. *2 BR24S16-W A1 becomes P1. *3 BR24S16-W A0 becomes P0.
Difference of slave address of each type
25/32
Software reset Software reset is executed when to avoid malfunction after power on, and to reset during command input. Software reset has several kinds, and 3 kids of them are shown in the figure below. (Refer to Fig.45(a), Fig.45(b), Fig.45(c).) In dummy clock input area, release the SDA bus ('H' by pull up). In dummy clock area, ACK output and read data '0' (both 'L' level) may be output from EEPROM, therefore, if 'H' is input forcibly, output may conflict and over current may flow, leading to instantaneous power failure of system power source or influence upon devices.
Dummy clockx14 Startx2
SCL SDA
1
2
13
14
Normal command Normal command
Fig.45-(a) The case of 14 Dummy clock + START + START+ command inpu
Start Dummy clockx9 Start
SCL SDA
1
2
8
9
Normal command Normal command
Fig.45-(b) The case of START+9 Dummy clock + START + command input
Startx9
SCL SDA
1
2
3
7
8
9
Normal command Normal command
Fig.45-(c) START x 9 + command input
* Start command from START input.
Acknowledge polling During internal write, all input commands are ignored, therefore ACK is not sent back. During internal automatic write execution after write cycle input, next command (slave address) is sent, and if the first ACK signal sends back 'L', then it means end of write action, while if it sends back 'H', it means now in writing. By use of acknowledge polling, next command can be executed without waiting for tWR = 5ms. When to write continuously, R/W = 0, when to carry out current read cycle after write, slave address R/W = 1 is sent, and if ACK signal sends back 'L', then execute word address input and data so forth.
During internal write,
First write command
S T A R T S T O P S T Slave A address R T A C K H
ACK = HIGH is sent back. S T Slave A R address T A C K H
Write command
...
tWR Second write command
S T Slave A R address T A C K H S T Slave A R address T A C K L Word address A C K L A C K L S T O P
...
Data
tWR After completion of internal write, ACK=LOW is sent back, so input next word address and data in succession.
Fig.46 Case to continuously write by acknowledge polling
26/32
WP valid timing (write cancel) WP is usually fixed to 'H' or 'L', but when WP is used to cancel write cycle and so forth, pay attention to the following WP valid timing. During write cycle execution, in cancel valid area, by setting WP='H', write cycle can be cancelled. In both byte write cycle and page write cycle, the area from the first start condition of command to the rise of clock to taken in D0 of data(in page write cycle, the first byte data) is cancel invalid area. WP input in this area becomes Don't care. Set the setup time to rise of D0 taken 100ns or more. The area from the rise of SCL to take in D0 to the end of internal automatic write (tWR) is cancel valid area. And, when it is set WP='H' during tWR, write is ended forcibly, data of address under access is not guaranteed, therefore, write it once again.(Refer to Fig.47.) After execution of forced end by WP standby status gets in, so there is no need to wait for tWR (5ms at maximum).
Rise of D0 taken clock
SCL SDA D1 D0 ACK
SCL
Rise of SDA
SDA
D0
Enlarged view S T Slave A R address T A A C Word C K address K D7 D6 D5 D4 D3 D2 D1 D0 L L A C K L
ACK Enlarged view A C K L S T O P
SDA
Data
tWR
WP cancel invalid area
WP cancel valid area
Write forced end
WP
Data is not written.
Data not guaranteed
Fig.47 WP valid timing
Command cancel by start condition and stop condition During command input, by continuously inputting start condition and stop condition, command can be cancelled. (Refer to Fig. 48.) However, in ACK output area and during data read, SDA bus may output 'L', and in this case, start condition and stop condition cannot be input, so reset is not available. Therefore, execute software reset. And when command is cancelled by start, stop condition, during random read cycle, sequential read cycle, or current read cycle, internal setting address is not determined, therefore, it is not possible to carry out current read cycle in succession. When to carry out read cycle in succession, carry out random read cycle.
SCL
SDA
1
0
1
0
Start condition Stop condition
Fig.48 Case of cancel by start, stop condition during slave address input
27/32
I/O peripheral circuit
Pull up resistance of SDA terminal
SDA is NMOS open drain, so requires pull up resistance. As for this resistance value (RPU), select an appropriate value to this resistance value from microcontroller VIL, IL, and VOL-IOL characteristics of this IC. If RPU is large, action frequency is limited. The smaller the RPU, the larger the consumption current at action.
Maximum value of RPU
The maximum value of RPU is determined by the following factors. (1)SDA rise time to be determined by the capacitance (CBUS) of bus line of RPU and SDA should be tR or below. And AC timing should be satisfied even when SDA rise time is late. (2)The bus electric potential A to be determined by input leak total (IL) of device connected to bus output of 'H' to SDA bus and RPU should sufficiently secure the input 'H' level (VIH) of microcontroller and EEPROM including recommended noise margin 0.2Vcc.
Vcc ILRPU 0.2Vcc VIH
from(2)
RPU
0.8VCCVIH IL
Microcontroller
RPU
BR24SXX
E.) When Vcc = 3V, IL=10A, VIH = 0.7Vcc,
A
SDA terminal
RPU
0.8x30.7x3 -6 10x10
IL
IL Bus line capacity CBUS
Minimum value of RPU
300 k
The minimum value of RPU is determined by the following factors. (1)When IC outputs LOW, it should be satisfied that VOLMAX=0.4V and IOLMAX=3mA.
Fig.49 I/O circuit diagram
VCCVOL IOL RPU RPU VCCVOL IOL
(2)VOLMAX=0.4V should secure the input 'L' level (VIL) of microcontroller and EEPROM including recommended noise margin 0.1Vcc. VOLMAX VIL-0.1 Vcc Ex.) When Vcc= 3V, VOL0.4V, IOL=3mA, microcontroller, EEPROM VIL=0.3Vcc from(1),
RPU
30.4 3x10 -3
867
And
VOL=0.4V VIL=0.3x3 =0.9V
Therefore, the condition (2) is satisfied.
Pull up resistance of SCL terminal
When SCL control is made at CMOS output port, there is no need, but in the case there is timing where SCL becomes 'Hi-Z', add a pull up resistance. As for the pull up resistance, one of several k ~ several ten k is recommended in consideration of drive performance of output port of microcontroller.
A0, A1, A2, WP process
Process of device address terminals (A0,A1,A2)
Check whether the set device address coincides with device address input sent from the master side or not, and select one among plural devices connected to a same bus. Connect this terminal to pull up or pull down, or Vcc or GND. And, pins(Don't use PIN) not used as device address may be set to any of 'H' , 'L', and 'Hi-Z'.
Types with Don't use PIN
BR24S16/F/FJ/FV/FVT/FVM/FVJ/NUX-W
A0, A1, A2
Process of WP terminal
WP terminal is the terminal that prohibits and permits write in hardware manner. In 'H' status, only READ is available and WRITE of all address is prohibited. In the case of 'L', both are available. In the case of use it as an ROM, it is recommended to connect it to pull up or Vcc. In the case to use both READ and WRITE, control WP terminal or connect it to pull down or GND.
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Cautions on microcontroller connection
Rs
In I2C BUS, it is recommended that SDA port is of open drain input/output. However, when to use CMOS input / output of tri state to SDA port, insert a series resistance Rs between the pull up resistance Rpu and the SDA terminal of EEPROM. This is controls over current that occurs when PMOS of the microcontroller and NMOS of EEPROM are turned ON simultaneously. Rs also plays the role of protection of SDA terminal against surge. Therefore, even when SDA port is open drain input/output, Rs can be used.
ACK
SCL RPU
RS
SDA
'H' output of microcontroller 'L' output of EEPROM
Microcontroller
EEPROM
Over current flows to SDA line by 'H' output of microcontroller and 'L' output of EEPROM.
Fig.50 I/O circuit diagram
Fig.51 Input/output collision timing
Maximum value of Rs
The maximum value of Rs is determined by following relations. (1)SDA rise time to be determined by the capacity (CBUS) of bus line of Rpu and SDA shoulder be tR or below. And AC timing should be satisfied even when SDA rise time is late. (2)The bus electric potential A to be determined by Rpu and Rs the moment when EEPROM outputs 'L' to SDA bus should sufficiently secure the input 'L' level (VIL) of microcontroller including recommended noise margin 0.1Vcc.
VCC RPU A RS IOL
Bus line capacity CBUS
(VCCVOL)xRS RPU+RS
VOL
+ VOL+0.1VCCVIL
RS
VILVOL0.1VCC 1.1VCCVIL
x
RPU
ExampleWhen VCC=3V,VIL=0.3VCC,VOL=0.4V,RPU=20k,
VIL
Microcontroller
EEPROM
from(2),
RS
0.3x30.40.1x3 x 1.1x30.3x3
20x10
3
Fig.52 I/O circuit diagram
1.67k
Maximum value of Rs
The minimum value of Rs is determined by over current at bus collision. When over current flows, noises in power source line, and instantaneous power failure of power source may occur. When allowable over current is defined as I, the following relation must be satisfied. Determine the allowable current in consideration of impedance of power source line in set and so forth. Set the over current to EEPROM 10mA or below.
VCC RS
'L' output
RPU RS
I VCC I
RS
Over current 'H' output
ExampleWhen VCC=3V, I=10mA RS 3 -3 10x10
Microcontroller
EEPROM
300
Fig.53 I/O circuit diagram
29/32
I2C BUS input / output circuit
Input (A0, A1, A2, SCL, WP)
Fig.54 Input pin circuit diagram
Input/Output (SDA)
Fig.55 Input /output pin circuit diagram
30/32
Notes on power ON At power on, in IC internal circuit and set, Vcc rises through unstable low voltage area, and IC inside is not completely reset, and malfunction may occur. To prevent this, functions of POR circuit and LVCC circuit are equipped. To assure the action, observe the following condition at power on.
1. Set SDA = 'H' and SCL ='L' or 'H' 2. Start power source so as to satisfy the recommended conditions of tR, tOFF, and Vbot for operating POR circuit.
VCC tR
Recommended conditions of tR,tOFF,Vbot tR tOFF Vbot
10ms or below 10ms or longer 0.3V or below
Vbot
tOFF 0
100ms or below 10ms or longer 0.2V or below
Fig.56 Rise waveform diagram 3. Set SDA and SCL so as not to become 'Hi-Z'. When the above conditions 1 and 2 cannot be observed, take the following countermeasures. a) In the case when the above conditions 1 cannot be observed. When SDA becomes 'L' at power on . Control SCL and SDA as shown below, to make SCL and SDA, 'H' and 'H'.
VCC SCL
tLOW
SDA
After Vcc becomes stable After Vcc becomes stable
tDH
tSU:DAT
tSU:DAT
Fig.57 When SCL='H' and SDA='L'
Fig.58 When SCL='H' and SDA='L'
b) In the case when the above condition 2 cannot be observed. After power source becomes stable, execute software reset(P26). c) In the case when the above conditions 1 and 2 cannot be observed. Carry out a), and then carry out b).
Low voltage malfunction prevention function LVCC circuit prevents data rewrite action at low power, and prevents wrong write. At LVCC voltage (Typ. =1.2V) or below, it prevent data rewrite. Vcc noise countermeasures Bypass capacitor When noise or surge gets in the power source line, malfunction may occur, therefore, for removing these, it is recommended to attach a by pass capacitor (0.1F) between IC Vcc and GND. At that moment, attach it as close to IC as possible. And, it is also recommended to attach a bypass capacitor between board Vcc and GND. Cautions on use (1)Described numeric values and data are design representative values, and the values are not guaranteed. (2)We believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further sufficiently. In the case of use by changing the fixed number of external parts, make your decision with sufficient margin in consideration of static characteristics and transition characteristics and fluctuations of external parts and our LSI. (3)Absolute maximum ratings If the absolute maximum ratings such as impressed voltage and action temperature range and so forth are exceeded, LSI may be destructed. Do not impress voltage and temperature exceeding the absolute maximum ratings. In the case of fear exceeding the absolute maximum ratings, take physical safety countermeasures such as fuses, and see to it that conditions exceeding the absolute maximum ratings should not be impressed to LSI. (4)GND electric potential Set the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltage is lower than that of GND terminal. (5)Terminal design In consideration of permissible loss in actual use condition, carry out heat design with sufficient margin. (6)Terminal to terminal shortcircuit and wrong packaging When to package LSI onto a board, pay sufficient attention to LSI direction and displacement. Wrong packaging may destruct LSI. And in the case of shortcircuit between LSI terminals and terminals and power source, terminal and GND owing to foreign matter, LSI may be destructed. (7)Use in a strong electromagnetic field may cause malfunction, therefore, evaluate design sufficiently.
31/32
Selection of order type
BR
2
4
S
2
5
6
F
Package
W
E
2
ROHM type BUS type 2 24I C name
Operating temperature
Capacity
16=16K 32=32K 64=64K 128=128K 256=256K
01=1K L:-40+85 02=2K S:-40+85 04=4K 08=8K
Package specifications
SOP8/SOP-J8/SSOP-B/TSSOP-B8/TSSOP-B8J
External appearance
F:SOP8 FJ:SOP-J8 FV : SSOP-B8 FVT : TSSOP-B8 FVM : MSOP8 FVJ : TSSOP-B8J NUX : VSON008X2030
Double cell Package specifications E2reel shape emboss taping TRreel shape emboss taping
SOP8
5.00.2 8 6.20.3 4.40.2 5
SOP-J8
4.90.2
SSOP-B8
3.00.2
8 5
TSSOP-B8
3.00.1 8 5 0.50.15 1.00.2
TSSOP-B8J
Package specifications Package type Emboss taping Package quantity 2500pcs(SOP8/SOP-J8/SSOP-B8/TSSOP-B8J)
3000pcs(TSSOP-B8)
0.45Min.
6.00.3 3.90.2
6.40.3 4.40.2
0.3Min.
8765
0.90.15 0.3Min.
Package direction E2
(When the reel is gripped by the left hand, and the tape is pulled out by the right hand, No.1 pin of the product is at the left top.
1.50.1 0.11
1.150.1 0.1
0.17 +0.1 -0.05
1.3750.1 0.175
0.595
1
4
1234
1
4
0.20.1 0.1
0.150.1
1.00.1 0.10.05
6.40.2
4.40.1 1
4
0.145 -0.03
+0.05
0.1 0.220.1 0.65
0.08 S 0.245 0.65
+0.05 -0.04
1.27 0.420.1
1.27 0.420.1
(0.52)
(Unit:mm)
Reel
Pin No.1
Pulling side
MSOP8
External appearance
2.9 0.1
For ordering, specify a number of multiples of the package quantity.
Package specifications Package type Package quantity Emboss taping 3000pcs
(When the reel is gripped by the left hand, and the tape is pulled out by the right hand, No.1 pin of the product is at the right top.
XX X X XXX XX X X XXX XX X X XX X XX X X XXX XX X X XXX
4.0 0.2
8
5
2.8 0.1
1
4
0.29 0.15 0.6 0.2
0.475
0.145 +0.05 -0.03 0.22
+0.05 -0.04
0.9Max. 0.75 0.05 0.08 0.05
Package direction TR Reel Pin No.1
Pulling side
0.08 M
0.65
0.08 S
(Unit:mm)
For ordering, specify a number of multiples of the package quantity.
VSON008X2030
External appearance Package specifications Package type Package quantity Emboss taping 4000pcs
(When the reel is gripped by the left hand, and the tape is pulled out by the right hand, No.1 pin of the product is at the right top.
Package direction TR Reel Pin No.1 Pulling side
(Unit:mm)
For ordering, specify a number of multiples of the package quantity.
32/32
Catalog No.08T504A '08.9 ROHM (c)
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products specified in this document are not designed to be radiation tolerant. While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law.
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http://www.rohm.com/contact/
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